lMG7420PLFC-X 240*128 dots features black on white film stn type transmissive mode high brightness cfl backlight high contrast lc material built-in lcd controller t6963c mechanical data item value unit module dimensions 159.4*101*11 mm viewing area 123*68 mm resolution 240*128 dots dot size 0.47*0.47 mm dot pitch 0.5*0.5 mm weight 180 g optical data item symbol condition min typ max unit contrast ratio k ?=10, q =0, note 1 -18- - brightness - t=25c, il=5ma, note 8 60.0 80.0 - cd/m 2 viewing direction - 6 oclock viewing angle ?2 - ?1 k=2, note 1 30 40 - degree response time (rise) t r ?=10, q =0, note 1 - 160 210 ms response time (fall) t f ?=10, q =0, note 1 - 110 160 ms absolute maximum ratings item symbol condition min max unit supply voltage (logic) v dd - v ss -06.5v supply voltage (lc drive) v dd - v ee - 0 20.5 v input voltage v i - -0.3 0.3+vdd v operating temperature t op note 5,6 0 50 c storage temperature t st note 7 -20 60 c data interface pin assignment pin no symbol level function a1 vss (0v) - ground a2 vdd (+5v) - power supply for logic circuit a3 v0 - power supply for lcd drive a4 c/d - not wr=low and c/d=high for command write, c/d= low for data write, not rd = low and c/d=high for status read, c/d = low for data read a5 not wr - dw=low for data write a6 not rd - rd=low for data read a7-a14 db0 - db7 - display data a15 not ce - chip enable (not ce must be low) a16 not ret - reset a17 vee (-15v) - power supply for lcd drive a18 not disp off - nc for display on, gnd fordisplay off a19 f/s - character font selection (f/s=high for 6x8 font, f/s=low for 8x8 font) a20 reverse - display mode reverse cfl interface pin assignment pin no symbol level function 1 gnd - cfl ground 2 nc - no connection 3 nc - no connection 4 hv - power supply for cfl electrical characteristics item symbol condition min typ max unit supply voltage (logic) v dd - v ss - 4.75 5.0 5.25 v supply voltage (lc drive) v ee - v ss - -14.5 -15.0 -15.5 v supply current i dd note 2 - 11.7 14.0 ma i ee note 2 - 2.5 4.0 ma input voltage (high level) v ih high level 0.8* vdd -vddv input voltage (low level) v il low level 0 - 0.2* vdd v frame frequency f flm note 4 - 75 - hz duty ratio - 1/128 - recommended lc drive voltage v dd -v o duty=1/128 t=0c, ?=10, note 3 - 16.9 - v duty=1/128 t=25c, ?=10, note 3 - 15.8 - v duty=1/128 t=50c, ?=10, note 3 - 15.2 - v backlight lamp voltage v bl t=25c - 360 - vrms backlight lamp frequency f bl t=25 c 30 70 85 khz backlight lamp current i bl t=25 c 2.5 5.0 5.5 marms lamp start voltage v s t=25c, note 9 (1000) - - v timing characteristics item symbol min typ max unit c/d set up time tcds 100 - - ns c/d hold time tchd 10 - - ns not ce, not rd, not wr pulse width not tce, not trd, not twr 80 - - ns data set up time tds 80 - - ns data hold time tdh 40 - - ns access time tacc - - 150 ns output hold time toh 10 - 50 ns inverter and connectors recommended inverter starter kit hitachi invc191 start74xx lamp connector lamp housing connector mitsumi m63m83-04 m61m73-04, m60-04-30-114p or m60-04-30-134p note1: definition of optical data, see page 84 note 2: fframe=75hz, vdd-v0=15.8v, ta=25c note 3: recommended lcd driving may fluctuate about +- 1.0v by each module. note 4: need to make sure of flickering and rippling of display when setting the frame frequency in your set. note 5: background colour of the lcd changes depending on temperature. between 40-50c optical characteristics of the lcd like contast and viewing angle change but the display remains readable. note 6: higher starting voltage of cfl and higher lcd driving voltage are needed while operating at 0c. the lifetime of cfl will be reduced at 0c note 7: storage at -20c < 48 hr, ta at 60c < 168 hr note 8: measurement after 10 minutes of cfl operating. brightness control:100% note 9: starting discharge voltage is increased when lcm is operating at lower temperature. please check the characteristics of inverter before applying. www..net
mechanical dimensions (50) (50) cn2 1 20 1 10 10.0 3.5 8.5 6.9 (2.015) 139.4 142.4 159.4 123.0 min 68.0 min 82.0 101.0 3.5 (3.015) 6.6 2.5 0.47 0.03 0.47 0.03 152.4+/-0.3 124.0+/-0.3 0.5*239+0.47=119.97+/-0.1 22.86+/-0.3 12.0+/-0.3 48.26+/-0.3 2.54+/-0.3 12.74+/-0.3 1 4 70.0+/-0.3 94.0+/-0.3 6.5+/-0.5 1.2+/-0.2 2.015 max 11.0 max. 0.5*127+0.47=63.97+/-0.1 2.54+/-0.3 1.515 max cn 3 note 1 cn 1 note : do not connect any signal to cn3 use cn1 as interface 4- ? 3.0 30- ? 1.0 block diagram power supply / power up timing diagram lcd 240*128 y1 y240 80 ic5 80 80 ic4 ic3 x128 x1 64 64 ic1 ic2 flm cl1 cl2 d1 13 8 ram osc 8 db0 db7 vdd vss v0 vee timing vlcd m' f/s ce ret c/d wr rd d1' power circuit controller t6369c vdd vss v0 vee +5v -15.0v vr lcm vr : 10-20k w vdd-v0 : lcd driving v o vdd signal vee 4.75v 0 ms min. vdd signa l vee 0 ms min. 5v valid data power on power off 0~50 ms 0~50 ms 4.75v interface timing diagram x1 x2 y1 y2 y3 y4 y5 y6 y7 y8 load x240 cp d3 d2 d1 1.4us min frm load frm y317 y320 y319 y318 d0 240*t 52.1ms |
